100 RTL Design Interview Questions

RTL Design Fundamentals

1. What is RTL (Register Transfer Level) Design?
2. Why is RTL Design important in ASIC/FPGA development?
3. Explain the RTL Design flow.
4. What is the difference between RTL and Gate-Level Design?
5. What are the responsibilities of an RTL Design Engineer?
6. What is synthesizable RTL?
7. What are RTL coding guidelines?
8. What is design hierarchy in RTL?
9. What is modular design?
10. What are reusable RTL blocks?

Verilog/SystemVerilog Basics

1. Difference between wire and reg.
2. Difference between logic and wire.
3. Difference between blocking (=) and non-blocking (<=) assignments.
4. When should blocking assignments be used?
5. When should non-blocking assignments be used?
6. What is always_comb?