100 UVM (Universal Verification Methodology) Interview Questions

UVM Fundamentals

1. What is UVM?
2. Why is UVM used in verification?
3. What are the advantages of UVM?
4. What is the difference between UVM and traditional Verilog testbenches?
5. What are the key features of UVM?
6. What is a UVM testbench architecture?
7. What are UVM base classes?
8. What is the UVM factory?
9. What is object-oriented programming (OOP) in UVM?
10. What are UVM phases?

UVM Components

1. What is a uvm_component?
2. What is a uvm_object?
3. Difference between uvm_component and uvm_object.
4. What is a UVM test?
5. What is a UVM environment (env)?
6. What is a UVM agent?