100 Verilog Interview Questions

Verilog Fundamentals

1. What is Verilog HDL?
2. Why is Verilog used in digital design?
3. What are the different abstraction levels in Verilog?
4. What is the difference between Behavioral, RTL, and Gate-Level modeling?
5. What are Verilog modules?
6. What is the structure of a Verilog module?
7. What is the purpose of ports in Verilog?
8. What are parameters in Verilog?
9. What is a synthesizable design?
10. What is a testbench?

Data Types & Operators

1. What is the difference between wire and reg?
2. What are Verilog net data types?
3. What are Verilog variable data types?
4. What is the difference between signed and unsigned data types?
5. What are vectors in Verilog?
6. What is concatenation in Verilog?