In Verilog, blocking (=) and non-blocking (<=) assignments are used inside procedural blocks (always, initial) to assign values to variables.
Understanding the difference is one of the most frequently asked RTL Design interview questions.
=)A blocking assignment executes sequentially. The next statement waits until the current assignment is completed.
always @(*) begin
a = b;
c = a;
end
a gets value of b
c gets updated value of a
So if:
b = 5
Then:
a = 5
c = 5
✅ Combinational Logic
always @(*) begin
y = a & b;
end
<=)