What is Metastability?

Metastability is a condition in a flip-flop where the output remains in an undefined or unstable state for a period of time instead of settling immediately to logic 0 or logic 1.

It typically occurs when the input data changes very close to the active clock edge, violating the setup time or hold time requirements.

Simple Definition

Metastability occurs when a flip-flop cannot decide whether its output should be a 0 or a 1 because setup or hold timing requirements have been violated.

Why Does Metastability Occur?

A flip-flop requires:

• Data to be stable before the clock edge (Setup Time)
• Data to remain stable after the clock edge (Hold Time)

If either requirement is violated:

Data changes too close to clock edge
          ↓
Setup/Hold Violation
          ↓
Metastability

Timing Diagram

Clock :  ____/‾‾‾\\____

Data  :  -----0---1----
                ↑
         Data changes
      near clock edge

Output:  ----?---------

Instead of becoming a clean 0 or 1, the output may remain uncertain for a short time.

What Happens During Metastability?